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DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale

ICLR 2025 · Graph learning › GNN architectures · approach: Physics-inspired GNNs · 0 citations (OpenAlex)

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Proposes DeepGate4, a graph transformer for circuit (AIG) representation learning that uses DAG-aware graph partitioning with level-ordered updating, a GAT-based sparse transformer, and a fused CUDA inference kernel to scale to million-gate circuits.

Problem

Circuit representation learning on large AIGs is limited by GNN over-squashing and the quadratic memory of dense graph transformers, and existing sub-linear GNN training (historical embeddings with random sampling) ignores the causal, level-ordered structure of DAGs.

Approach

Partition AIGs into k-depth logic cones and encode them level by level with intra-level and inter-level historical-embedding updates so each gate is computed once; replace multi-head attention with GAT over virtual cone edges plus global/local structural encodings, and add a gradient-based multi-task loss balancer and a fused CUDA kernel exploiting AIG in-degree sparsity.

Key results

• DeepGate4 reports overall loss L_all of 3.16 on ITC99 vs 3.73 for DeepGate3-dagger, and reduces overall loss by 15.5% (ITC99) and 31.1% (EPFL) over the second-best method.
• Fused-DeepGate4 reduces inference time by 35.1% and memory by 46.8% relative to DeepGate4 on average.
• DeepGate4 trained on ~15K-gate average circuits generalizes to a 402K-gate Image_Processing design with stable performance, and its memory stays constant beyond a certain circuit size while GNN memory grows linearly.

Measured effects reported in the paper

Surprising findings

• Dense-attention and sparse transformer baselines (GraphGPS, Exphormer, DAGformer) run out of memory on ITC99 without the proposed partitioning, while GNNs use 30-40 GB.
• Larger cone depth k increases memory strongly and degrades structural task performance.

Limitations

• Inference runtime remains slower than GNNs because graph transformers encode cones level by level.
• Structural-task performance depends on cone depth k and overlap stride, with larger k hurting structural losses.
• Some improvements are reported against dagger-modified baselines rather than original implementations.

Experimental setup

Datasets: ITC99 EPFL random control OpenABC-D

Benchmarks: ITC99 EPFL random control OpenABC-D SAT solving (CaDiCaL)

Metrics: multi-task loss L_all gate-level and graph-level task losses connection prediction accuracy inference time (s) memory (MB/GB) average precision PR-AUC SAT solving time

Baselines: GCN GraphSAGE GAT PNA GraphGPS Exphormer DAGformer DeepGate2 DeepGate3 PolarGate HOGA-5

Builds on: DeepGate3 DeepGate2 DAGformer Fused-GAT GNNAutoScale

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