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A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design
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Proposes PruneX, a data-driven logic synthesis operator paradigm that uses a learned classifier to skip ineffective node-level transformations, with a circuit domain generalization framework (COG) to handle distribution shift across circuits.
Problem
Logic synthesis operators (Resub, Mfs2) spend most runtime on ineffective node-level transformations; learned classifiers that prune these must generalize out-of-distribution to unseen circuits.
Approach
Formulate cross-circuit OOD generalization as circuit domain generalization: aggregate circuit datasets into domains, learn domain-invariant bipartite subgraph embeddings (KDSR) per node, and use a multi-head domain-aware distributional classifier (DADC), then keep top-k scored nodes for transformation.
Key results
- PruneX-COG achieves up to 3.1x faster runtime (Resub on Hyp under Strategy 1) while keeping comparable size.
- On Mfs2, PruneX-COG improves average runtime by 40.96% (Strategy 1) and 26.66% (Strategy 2) with 0.36% and 0.07% size degradation.
- Applying PruneX-COG twice (2PruneX-COG, k=40%) reduces size/depth by 7.24% on average and runtime by 17% on open-source circuits.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Prune ineffective node-level transformations with PruneX-COG | Mfs2 · EPFL and IWLS, Evaluation Strategy 1 | runtime: 40.96% | Helped |
| Prune ineffective node-level transformations with PruneX-COG | Mfs2 · EPFL and IWLS, Evaluation Strategy 2 | runtime: 26.66% | Helped |
| Prune ineffective node-level transformations with PruneX-COG | Mfs2 · EPFL and IWLS | circuit size: 0.36%; 0.07% | Hurt |
| Prune ineffective node-level transformations with PruneX-COG | Resub · EPFL and IWLS | runtime: 54.22% | Helped |
| Prune ineffective node-level transformations with PruneX-COG | Resub · EPFL and IWLS | circuit size: 0.35% | Hurt |
| Apply PruneX-COG twice with k=40% | Mfs2 · Open-source circuits | runtime: 17% | Helped |
| Apply PruneX-COG twice with k=30% | Mfs2 · Open-source circuits | circuit size/depth: 6.9% | Helped |
| Apply PruneX-COG twice with k=30% | Mfs2 · Open-source circuits | runtime: 40.02% | Helped |
| Add DADC and circuit-domain-aware classification (ablation) | PruneX-COG · Mfs2 and Resub, Log2, Hyp, Multiplier, and Sin | top 50% accuracy: See Ablation Study table | Helped |
| Add KDSR instead of manually designed features (ablation) | PruneX-COG · Mfs2 and Resub, Log2, Hyp, Multiplier, and Sin | top 50% accuracy: See Ablation Study table | Helped |
| Apply PruneX-COG twice with k=40% | Mfs2 · Industrial circuits | runtime: 8.7% | Hurt |
Surprising findings
- Without the knowledge-driven subgraph representation, top-50% recall on Log2 with Mfs2 falls to 0.08, showing representation choice is critical.
- Some configurations (k=40%) on industrial circuits increase runtime versus k=30%, e.g., -29.67% time change on d3151.
Limitations
- Recall drop reduces QoR, so top-k must be set high enough; trade-off between runtime and QoR via k.
- Evaluated only on Resub and Mfs2 operators with the ABC backend in experiments.
- Industrial results show mixed runtime and QoR at larger k.
Experimental setup
Datasets: EPFL benchmark IWLS benchmark Huawei HiSilicon industrial circuits
Benchmarks: EPFL IWLS Huawei HiSilicon industrial circuits
Metrics: top-k recall runtime node count (size) depth (level)
Baselines: Random EnsembleMLP Default Mfs2 Default Resub PruneX-COG without DADC PruneX-COG without DADC and KDSR
Builds on: ABC Focal Loss domain generalization
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