Research map / Graph learning / Graph self-supervised learning
AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling
Read the paperCheck your idea against 108,967 papers
AI-extracted summary. Written by AI from the paper's full text. Numbers and claims can be wrong or missing context, so check the paper before you cite or build on it.
Proposes AnalogGenie-Lite, a small decoder-only transformer that generates analog circuit topologies using a pruned device-pin graph, mined frequent subgraph tokens, and Chinese Postman Eulerian sequences, improving scalability and validity over prior methods.
Problem
Generating novel analog IC topologies is hard: text and prior graph representations are error-prone, scale poorly with device count, and produce long sequences that limit transformer-based generation.
Approach
Combines three lightweight graph-modeling steps: removing device-self nodes and using n-1 edges for shared nets (O(n) instead of O(n^2)), mining frequent subgraphs with gSpan and replacing them with pin tokens, and encoding the circuit as a Chinese Postman (minimum-duplication Eulerian) closed walk.
Key results
- Achieves 97% validity for 1000 generated topologies versus 63.4%-82% for prior methods (23.5%-33.6% improvement).
- Scales to circuits with 324 devices, a 5.15x to 71.11x improvement over prior methods.
- Sequence compression of 71.11x over adjacency matrices and 5.15x over AnalogGenie; op-amp FoM 15017.7 vs 13744.8 for AnalogGenie.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Replace AnalogGenie's graph representation with lightweight graph pruning (ablation) | AnalogGenie-Lite · Analog circuit topology generation | validity (%): 73.5 -> 80.1 | Helped |
| Add frequent-subgraph mining and subgraph simplification (ablation) | AnalogGenie-Lite (Graph) · Analog circuit topology generation | validity (%): 80.1 -> 87.3 | Helped |
| Use optimal Chinese Postman sequence modeling (ablation) | AnalogGenie-Lite (Graph+Subgraph) · Analog circuit topology generation | validity (%): 87.3 -> 97 | Helped |
| Use lightweight graph pruning, frequent-subgraph simplification, and optimal sequence modeling | AnalogGenie-Lite · Analog circuit topology generation | scalability (devices): 63 -> 324 | Helped |
| Use lightweight graph pruning, frequent-subgraph simplification, and optimal sequence modeling | AnalogGenie-Lite · Analog circuit topology generation | validity (%): 73.5 -> 97 | Helped |
| Add frequent-subgraph mining and subgraph simplification (ablation) | AnalogGenie-Lite (Graph) · Analog circuit topology generation | scalability (devices): 183 -> 227 | Helped |
| Use optimal Chinese Postman sequence modeling (ablation) | AnalogGenie-Lite (Graph+Subgraph) · Analog circuit topology generation | scalability (devices): 227 -> 324 | Helped |
| Use lightweight graph pruning, frequent-subgraph simplification, and optimal sequence modeling | AnalogGenie-Lite · Op-Amp | FoM: 13744.8 -> 15017.7 | Helped |
| Use lightweight graph pruning, frequent-subgraph simplification, and optimal sequence modeling | AnalogGenie-Lite · Power converter | FoM: 3.3 -> 4.02 | Helped |
| Use lightweight graph pruning, frequent-subgraph simplification, and optimal sequence modeling | AnalogGenie-Lite · Analog circuit topology generation | MMD: 0.0532 -> 0.0408 | Helped |
Surprising findings
- Compression benefit varies substantially across circuit types, with PA circuits having unique structures that benefit less from subgraph reuse.
Limitations
- Subgraph simplification only applied when isolated-node count exceeds a threshold; subgraph mining generality across diverse datasets remains open.
- Compression is less effective for circuits with unique structures such as PAs.
- Cross-domain results show denser graphs (community, molecule) remain harder to compress.
Experimental setup
Datasets: AnalogGenie circuit topology database (3350 topologies, 11 types) protein graphs ego graphs community graphs molecule graphs 3D point cloud graphs
Benchmarks: analog circuit topology generation validity/scalability/novelty/performance on 3350-topology database cross-domain graph compression on protein, ego, community, molecule, 3D point cloud graphs
Metrics: validity scalability (max devices) versatility novelty (diff circuit %) MMD FoM sequence compression ratio
Baselines: AnalogCoder Artisan CktGNN LaMAGIC AnalogGenie
Builds on: AnalogGenie gSpan Chinese Postman Problem
Closest papers by meaning
- AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies (ICLR 2025 · similarity 0.93)
- AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding (NeurIPS 2026 · similarity 0.91)
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits (ICML 2024 · similarity 0.91)
- LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation (ICML 2025 · similarity 0.88)
- AnalogCoder: Analog Circuit Design via Training-Free Code Generation (AAAI 2025 · similarity 0.86)
- DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale (ICLR 2025 · similarity 0.85)
Writing a paper in this area? scime draft is a free LaTeX editor with AI included, real-time co-authors and a check of your references and venue rules before you submit. It also imports OpenAI Prism projects.