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CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
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Introduces CircuitFusion, a multimodal (HDL code, structural graph, functionality summary) circuit encoder pre-trained with four self-supervised tasks on sub-circuits split at register boundaries, with retrieval-augmented inference for PPA prediction.
Problem
Existing AI-assisted IC design methods are task-specific or use only graph-structured circuit representations, ignoring other circuit modalities such as HDL code and functional summaries; early RTL-stage design quality prediction remains hard.
Approach
Splits each RTL circuit into register-bounded sub-circuits encoded in three modalities, fuses them with a summary-centric cross-attention encoder, aligns RTL embeddings with netlist embeddings for implementation awareness, and uses retrieval of similar known circuits' metrics to enable fine-tuning and zero-shot prediction.
Key results
- CircuitFusion achieves MAPE of 12% (slack), 11% (WNS), 15% (TNS), 13% (power), and 11% (area), outperforming RTL-Timer, MasterRTL, SNS v2 and software/text encoders on all five tasks.
- Zero-shot top-1 retrieval gives slack MAPE of 21% for CircuitFusion versus 50-57% for software code encoders and LLM encoder.
- Applying S1 and S4 to baseline encoders such as NV-Embed-v1 reduces WNS MAPE from 26% to 17% and power MAPE from 44% to 20%.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use CircuitFusion instead of the strongest task-specific baseline | register slack prediction · Register slack prediction | MAPE: 17% -> 12% | Helped |
| Use CircuitFusion instead of the strongest baseline | WNS prediction · WNS prediction | MAPE: 16% -> 11% | Helped |
| Use CircuitFusion instead of the strongest baseline | TNS prediction · TNS prediction | MAPE: 25% -> 15% | Helped |
| Use CircuitFusion instead of the strongest baseline | total power prediction · Total power prediction | MAPE: 26% -> 13% | Helped |
| Use CircuitFusion instead of the strongest baseline | total area prediction · Total area prediction | MAPE: 16% -> 11% | Helped |
| Use CircuitFusion embeddings for top-1 similar-circuit retrieval instead of CodeSage | zero-shot slack prediction · Slack (zero-shot retrieval, top-1) | MAPE: 50 -> 21 | Helped |
| Use CircuitFusion embeddings for top-1 similar-circuit retrieval instead of CodeT5+ Embedding | zero-shot sub-circuit power prediction · Sub-circuit power (zero-shot retrieval, top-1) | MAPE: 88 -> 36 | Helped |
| Use CircuitFusion embeddings for top-1 similar-circuit retrieval instead of CodeT5+ Embedding | zero-shot sub-circuit area prediction · Sub-circuit area (zero-shot retrieval, top-1) | MAPE: 87 -> 35 | Helped |
| Add sub-circuit generation and retrieval-augmented inference (S1 and S4) | NV-Embed-v1 · WNS prediction | MAPE: 26% -> 17% | Helped |
| Add sub-circuit generation and retrieval-augmented inference (S1 and S4) | NV-Embed-v1 · TNS prediction | MAPE: 55% -> 27% | Helped |
| Add sub-circuit generation and retrieval-augmented inference (S1 and S4) | NV-Embed-v1 · Power prediction | MAPE: 44% -> 20% | Helped |
| Add sub-circuit generation and retrieval-augmented inference (S1 and S4) | NV-Embed-v1 · Area prediction | MAPE: 24% -> 17% | Helped |
Surprising findings
- Zero-shot retrieval-based prediction from CircuitFusion achieves reasonable accuracy without any task labels.
- Text and software code encoders achieve high TNS correlation (0.95-0.97) yet large MAPE (43-55%), indicating correlation alone is misleading.
Limitations
- Training data is limited (41 RTL designs) compared to what a robust circuit foundation model would need.
- Summary generation relies on GPT-4o, and the code encoder is frozen NV-Embed-v1, which constrains the representation.
- Evaluated only on five post-synthesis PPA prediction tasks with a single set of 8 test designs.
Experimental setup
Datasets: ITC'99 OpenCores VexRiscv Chipyard
Benchmarks: register slack prediction WNS prediction TNS prediction total power prediction total area prediction
Metrics: R MAPE
Baselines: RTL-Timer MasterRTL SNS v2 NV-Embed-v1 UnixCoder CodeT5+ Encoder CodeSage
Builds on: Graphormer GraphMAE InfoNCE mixup MasterRTL
Closest papers by meaning
- DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale (ICLR 2025 · similarity 0.89)
- Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment (ICLR 2025 · similarity 0.88)
- DeepLayout: Learning Neural Representations of Circuit Placement Layout (ICML 2025 · similarity 0.88)
- AnalogCoder: Analog Circuit Design via Training-Free Code Generation (AAAI 2025 · similarity 0.87)
- Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization (ICLR 2024 · similarity 0.87)
- A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design (ICML 2024 · similarity 0.86)
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