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Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
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Proposes MGVGA, a constrained masked modeling paradigm for AIG circuit representation learning that masks gates in latent space (MGM) and aligns masked AIGs with equivalent Verilog code embeddings from an LLM (VGA), evaluated on QoR prediction and logic equivalence identification.
Problem
Masked modeling on AIG circuits destroys logical equivalence and existing paradigms emphasize structure over abstract circuit function, so GNN circuit representations lack either fine-grained structure or functional semantics.
Approach
Mask gates in the encoder's latent space so the AIG keeps its logic during encoding, and align masked AIG representations via cross-attention with embeddings of logically equivalent Verilog code from an LLM, so reconstruction is constrained by function.
Key results
- On QoR prediction, MGVGA reaches average NDCG@3 of 0.540 vs 0.334 for DeepGate2.
- On logic equivalence identification, MGVGA achieves average F1 0.470 and AUC 0.862 vs DeepGate2's 0.424 and 0.804.
- Ablation shows the original masked modeling baseline gets NDCG@3 of 0.153 vs 0.540 for full MGVGA.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Replace original masked modeling with masked gate modeling (MGM) in latent space, masking ratio 0.3 (ablation) | DeepGCN AIG encoder · QoR prediction (10 designs) | NDCG@3: 0.153 -> 0.338 | Helped |
| Add Verilog-AIG alignment (VGA) on top of MGM (ablation) | DeepGCN AIG encoder · QoR prediction (10 designs) | NDCG@3: 0.338 -> 0.540 | Helped |
| Add MGM and VGA (full MGVGA) vs original masked modeling (ablation) | DeepGCN AIG encoder · Logic equivalence identification (10 designs) | AUC: 0.790 -> 0.862 | Helped |
| Add VGA on top of MGM (ablation) | DeepGCN AIG encoder · Logic equivalence identification (10 designs) | F1-Score: 0.433 -> 0.470 | Helped |
| Full MGVGA vs DeepGate2 baseline | AIG GNN representation · QoR prediction (10 designs) | Top-10% Commonality: 0.226 -> 0.301 | Helped |
| Full MGVGA vs DeepGate2 baseline | AIG GNN representation · Logic equivalence identification (10 designs) | AUC: 0.804 -> 0.862 | Helped |
| Increase MGM masking ratio from 0.3 to 0.5 or 0.7 (ablation) | MGVGA (VGA ratio 0.5) · QoR prediction (10 designs) | NDCG@3: 0.540 -> 0.438 (0.5), 0.400 (0.7) | Hurt |
| Increase VGA masking ratio from 0.3 to 0.5 (ablation) | MGVGA (MGM ratio 0.3) · Logic equivalence identification (10 designs) | F1-Score: 0.430 -> 0.470 | Helped |
| Increase VGA masking ratio from 0.5 to 0.7 (ablation) | MGVGA (MGM ratio 0.3) · QoR prediction (10 designs) | NDCG@3: 0.540 -> 0.498 | Hurt |
| Replace DeepGCN encoder with GraphSAGE or graph transformer under MGVGA (ablation) | GraphSAGE / graph transformer · QoR prediction (10 designs) | NDCG@3: 0.540 -> 0.469 (GraphSAGE), 0.452 (graph transformer) | Hurt |
| Apply MGVGA training to GraphSAGE and graph transformer instead of DeepGCN | GraphSAGE, graph transformer · Logic equivalence identification (10 designs) | F1-Score: GraphSAGE 0.455, graph transformer 0.450 vs DeepGate2 0.424 | Helped |
| Adding single-input AND gate augmentation during training | MGVGA training · QoR prediction and logic equivalence | not reported | No clear effect |
Surprising findings
- Original masked modeling on circuits performs poorly (NDCG@3 0.153), below the DeepGate2 baseline.
Limitations
- Relies on a single baseline (DeepGate2) for main comparison, with DeepGate3 only on small designs.
- Evaluation of SAT solving uses few designs and a reported SAT runtime that is inconsistent in places (e.g., a missing percentage).
Experimental setup
Datasets: MIT LL CEP ITC'99 IWLS'05 EPFL OpenCore Verilog source codes
Benchmarks: QoR prediction on 10 circuit designs logic equivalence identification on 10 designs SAT solving runtime acceleration
Metrics: NDCG@k Top-k% Commonality precision recall F1-score AUC runtime reduction
Baselines: DeepGate2 DeepGate3 GraphSAGE Graph Transformer original masked modeling
Builds on: DeepGate2 masked graph autoencoder DeepGCN gte-Qwen2-7B-instruct
Closest papers by meaning
- DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale (ICLR 2025 · similarity 0.90)
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR 2025 · similarity 0.88)
- DeepLayout: Learning Neural Representations of Circuit Placement Layout (ICML 2025 · similarity 0.87)
- BetterV: Controlled Verilog Generation with Discriminative Guidance (ICML 2024 · similarity 0.86)
- A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design (ICML 2024 · similarity 0.85)
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits (ICML 2024 · similarity 0.85)
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