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BetterV: Controlled Verilog Generation with Discriminative Guidance

ICML 2024 · Large language models › Agents, code and math · approach: LLMs for optimization and heuristics · 9 citations (OpenAlex)

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Fine-tunes code LLMs on processed Verilog data with C-alignment instruct-tuning and guides generation with task-specific generative discriminators (GeDi-style Bayes-rule decoding) for functional, syntactic, synthesis-size and SAT-runtime objectives.

Problem

LLMs for Verilog generation lack domain knowledge and scarce Verilog data, and they do not optimize downstream EDA objectives (synthesis netlist size, formal verification runtime) or functional/syntactic correctness during generation.

Approach

Instruct-tune LLMs on Verilog-C translation pairs and Verilog definition-body completion, augment data with the fine-tuned model filtered by Yosys, and train a small generative discriminator (control and anti-control codes) whose Bayes-rule guidance steers decoding toward task-specific desired Verilog attributes.

Key results

• BetterV-CodeQwen reaches 68.1 pass@1 on VerilogEval-machine and 46.1 pass@1 on VerilogEval-human, exceeding GPT-4 (60.0 and 43.5) by 8.1 and 2.6 points.
• Synthesis-guided BetterV yields on average 46.52% fewer AIG netlist nodes than the reference and 31.68% fewer than BetterV-base on the selected VerilogEval-human problems.
• Verification-guided BetterV reduces SAT solving time by 22.45% versus reference Verilog and 13.99% versus BetterV-base on selected ANSI-C designs.

Measured effects reported in the paper

Surprising findings

• The discriminator trained on one model's data also improved the original CodeLlama-7B-Instruct on functional correctness (pass@1 from 18.2 to 20.3), suggesting transfer across LLMs sharing a vocabulary.

Limitations

• Requires token-level probabilities, so it does not apply to closed-source models such as GPT-4.
• Guidance adds non-negligible computational overhead at decoding time.
• Downstream EDA evaluation is limited to a few selected problems and designs, with per-task hyperparameters (lambda, w, rho, tau) tuned differently per task.

Experimental setup

Datasets: VerilogEval GitHub Verilog/SystemVerilog repositories ANSI-C benchmarks

Benchmarks: VerilogEval-machine VerilogEval-human ANSI-C benchmarks (SAT runtime)

Metrics: pass@1 pass@5 pass@10 AIG node count SAT solving time

Baselines: GPT-3.5 GPT-4 CodeLlama-7B-Instruct DeepSeek-Coder-6.7b-Instruct CodeQwen1.5-7B-Chat ChipNeMo Thakur et al. VerilogEval RTLCoder

Builds on: GeDi PPLM DeepSpeed-Chat LoRA VerilogEval

Closest papers by meaning

• VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification (NeurIPS 2025 · similarity 0.89)
• VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool (AAAI 2025 · similarity 0.89)
• DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model (ICLR 2025 · similarity 0.88)
• QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation (NeurIPS 2025 · similarity 0.88)
• QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation (NeurIPS 2025 · similarity 0.87)
• CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair (ICLR 2025 · similarity 0.86)