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Bridging Layout and RTL: Knowledge Distillation based Timing Prediction
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Proposes RTLDistil, a cross-stage knowledge distillation framework in which a layout-level netlist GNN teacher transfers timing knowledge to a lightweight RTL-level SOG GNN student via node, subgraph, and global distillation losses, for RTL-stage arrival time, WNS and TNS prediction.
Problem
Early RTL-stage timing prediction is inaccurate because RTL representations lack physical parasitic information, while layout-level STA is too slow for rapid design iterations.
Approach
Transfers physical timing knowledge from a layout-aware GAT teacher to an RTL SOG GAT student through multi-granularity distillation (node-level DFF embedding alignment, fan-in-cone subgraph alignment, and global graph alignment), plus asynchronous forward-reverse propagation.
Key results
- RTLDistil reaches AT PCC 0.9227 and MAPE 16.87%, versus RTL-Timer's 0.8782 and 23.39% and MasterRTL's 0.3498.
- On TNS, RTLDistil achieves PCC 0.9586 versus RTL-Timer's 0.8451.
- Without distillation the student reaches AT MAPE 22.04%; the layout teacher reaches 11.20%, giving an upper bound.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| replace RTL-Timer with RTLDistil for timing prediction | RTL-level timing prediction · Arrival Time (AT) | PCC: 0.8782 -> 0.9227 | Helped |
| replace RTL-Timer with RTLDistil for timing prediction | RTL-level timing prediction · Arrival Time (AT) | MAPE: 23.39% -> 16.87% | Helped |
| replace RTL-Timer with RTLDistil for timing prediction | RTL-level timing prediction · Worst Negative Slack (WNS) | PCC: 0.8812 -> 0.9066 | Helped |
| replace RTL-Timer with RTLDistil for timing prediction | RTL-level timing prediction · Total Negative Slack (TNS) | PCC: 0.8451 -> 0.9586 | Helped |
| add knowledge distillation to the RTL student (ablation) | RTLDistil · Arrival Time (AT) | MAPE: 22.04% -> 17.77% | Helped |
| add downstream fine-tuning after knowledge distillation (ablation) | RTLDistil · Arrival Time (AT) | MAPE: 17.77% -> 16.87% | Helped |
| use node-level distillation only (ablation) | RTLDistil · Arrival Time (AT) | MAPE: -5.64% | Helped |
| use node- and global-level distillation without subgraph-level distillation (ablation) | RTLDistil · Arrival Time (AT) | PCC: 0.0254 | Helped |
| use subgraph- and global-level distillation without node-level distillation (ablation) | RTLDistil · Arrival Time (AT) | PCC: 0.0071 | Helped |
| use all three distillation levels: node, subgraph, and global (ablation) | RTLDistil · Arrival Time (AT) | PCC: 0.0440 | Helped |
| use all three distillation levels: node, subgraph, and global (ablation) | RTLDistil · Worst Negative Slack (WNS) | R2: 0.1222 | Helped |
| use all three distillation levels: node, subgraph, and global (ablation) | RTLDistil · Total Negative Slack (TNS) | MAPE: -2.36% | Helped |
Surprising findings
- Node-level distillation alone yields a slightly negative change in AT PCC (-0.0038), so the full multi-granularity combination is needed for correlation gains.
Limitations
- Evaluated on a self-collected dataset of 2004 designs that is not stated as released.
- Loss weights set to equal values from coarse grid search; sensitivity is only briefly noted.
- Future work needed for large SoC designs, multi-clock domains, and power/area objectives.
Experimental setup
Datasets: 2004 RTL designs from GitHub, Hugging Face, OpenCore, RISC-V projects, with back-end layouts from Synopsys Design Compil
Benchmarks: internal 2004-design RTL timing dataset (test split)
Metrics: PCC R2 MAPE
Baselines: MasterRTL RTL-Timer
Builds on: knowledge distillation graph attention network MasterRTL RTL-Timer
Closest papers by meaning
- PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling (AAAI 2024 · similarity 0.84)
- SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning (NeurIPS 2025 · similarity 0.83)
- DeepLayout: Learning Neural Representations of Circuit Placement Layout (ICML 2025 · similarity 0.83)
- DeepGate4: Efficient and Effective Representation Learning for Circuit Design at Scale (ICLR 2025 · similarity 0.83)
- CircuitSense: A Hierarchical Circuit System Benchmark Bridging Visual Comprehension and Symbolic Reasoning in Engineering Design Process (ICLR 2026 · similarity 0.83)
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR 2025 · similarity 0.83)
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