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CircuitSense: A Hierarchical Circuit System Benchmark Bridging Visual Comprehension and Symbolic Reasoning in Engineering Design Process

ICLR 2026 · Vision-language and multimodal › Multimodal LLMs · approach: Chain-of-thought multimodal reasoning

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Introduces CircuitSense, a hierarchical benchmark (8,006 problems) of visual circuit and block-diagram understanding with symbolic equation ground truth, and evaluates eight MLLMs across perception, analysis and design tasks.

Problem

MLLMs' ability to extract symbolic mathematical models (transfer functions, nodal equations) from circuit schematics and block diagrams across abstraction levels is untested; existing visual circuit benchmarks focus on recognition or shallow calculation.

Approach

A benchmark combining curated textbook/course problems with synthetic grid-based circuit schematics (SPICE/Lcapy-validated) and random block diagrams (Mason's gain formula) that have auto-derived symbolic ground truth, scored with SymPy-based equivalence checking, organized over six hierarchy levels and three task categories.

Key results

Surprising findings

Limitations

Experimental setup

Datasets: curated textbook and university course problems AnalogGenie ZeroSim synthetic schematic and block diagram problems

Benchmarks: CircuitSense

Metrics: accuracy symbolic equivalence (SymPy, numerical validation)

Baselines: GPT-4o GPT-4o-mini Claude-Sonnet-4 InternVL3-78B Qwen2.5-VL-72B-Instruct GLM-4.5V Gemma-3-27B

Builds on: MAPS Lcapy Mason's gain formula SPICE

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