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SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning
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Proposes SymRTLO, a neuron-symbolic framework that combines GPT-4o-driven rule retrieval, AST templates, and LLM-generated FSM minimization scripts to optimize Verilog RTL for PPA, evaluated against GPT baselines and RTLRewriter.
Problem
LLM-based RTL code optimization often fails to align generated Verilog with intended optimization rules and objectives, and relies on repeated slow synthesis feedback; compiler-based tools struggle with complex constraints and partially specified FSMs.
Approach
Combine a goal-conditioned retrieval-augmented library of optimization rules with AST-based rewrite templates (applied by the LLM) for data-flow optimization, and an LLM-generated symbolic FSM minimization script for control-flow optimization, followed by LLM testbench filtering and formal equivalence checking.
Key results
- On the RTLRewriter wire/cell benchmark, SymRTLO achieves GeoMean ratios of 0.63 (wires) and 0.67 (cells) versus the baseline, beating RTLRewriter's reported 0.69 and 0.77.
- Pass@1 of 97.5% for SymRTLO versus 45.9% for GPT-4o.
- On FSM designs, SymRTLO improves power, time, and area by up to 50.59%, 12.65%, and 53.09% over RTLRewriter, per the paper's text.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use SymRTLO’s retrieval-guided symbolic optimization instead of GPT-4o alone | RTL code optimization · RTL-Rewriter benchmark | Pass@1: 45.9 -> 97.5 | Helped |
| Use SymRTLO instead of RTLrewriter | RTL-Rewriter benchmark · RTL-Rewriter benchmark | Wires GeoMean: 0.69$^\dagger$ -> 0.63 | Helped |
| Use SymRTLO instead of RTLrewriter | RTL-Rewriter benchmark · RTL-Rewriter benchmark | Cells GeoMean: 0.77$^\dagger$ -> 0.67 | Helped |
| Apply SymRTLO FSM optimization instead of the original design | FSM designs · example1_state | Area: 833.0 -> 403.9 | Helped |
| Apply SymRTLO FSM optimization instead of the original design | FSM designs · example2_state | Time: 2.25 -> 1.17 | Helped |
| Apply SymRTLO algorithm optimization instead of the original design | Algorithm designs · sppm_redundancy | Power: 2.86 -> 1.77 | Helped |
| Apply SymRTLO algorithm optimization instead of the original design | Algorithm designs · subexpression_elim | Time: 11.09 -> 2.87 | Helped |
| Apply SymRTLO algorithm optimization instead of GPT-4o | Algorithm designs · subexpression_elim | Area: 8984.61 -> 7358.8 | Helped |
| Add the AST-based module (ablation) | SymRTLO · PPA test cases | PPA improvement | Helped |
| Add the FSM symbolic system (ablation) | SymRTLO · PPA test cases | PPA improvement | Helped |
| Add the goal-based search engine (ablation) | SymRTLO · PPA test cases | PPA improvement | Helped |
Surprising findings
- GPT-O1 produced an under-optimized FSM (10 states vs. 4 for the algorithm-driven design), showing that a strong commercial LLM struggles to follow a state-reduction algorithm.
Limitations
- The exact RTLRewriter test cases were not released, and the PPA comparison relies on unknown libraries, so results are hard to reproduce.
- Evaluation covers a small set of circuits (about 11 short benchmarks plus 10 FSM and algorithm cases), with area as the main optimization goal.
- The framework depends on proprietary GPT-4o and Synopsys tools.
Experimental setup
Datasets: RTLRewriter benchmark
Benchmarks: RTLRewriter benchmark
Metrics: pass@k wires cells power (mW) delay (ns) area (um^2)
Baselines: GPT-4o GPT-4-Turbo GPT-3.5-Turbo GPT-4o-mini GPT-O1 RTLCoder-DeepSeek RTLRewriter VeriGen
Builds on: RTLRewriter Pyverilog
Closest papers by meaning
- QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation (NeurIPS 2025 · similarity 0.86)
- PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Boards (PCB) Schematic Design with Structured Verification (NeurIPS 2026 · similarity 0.86)
- QiMeng-NeuComBack: Self-Evolving Translation from IR to Assembly Code (NeurIPS 2025 · similarity 0.85)
- AnalogCoder: Analog Circuit Design via Training-Free Code Generation (AAAI 2025 · similarity 0.85)
- QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation (NeurIPS 2025 · similarity 0.84)
- BetterV: Controlled Verilog Generation with Discriminative Guidance (ICML 2024 · similarity 0.84)
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