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AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies
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Proposes AnalogGenie, a GPT-style model that generates analog circuit topologies by sequentially predicting device pins along Eulerian circuits of pin-level graphs, trained on a 3350-topology dataset with Eulerian-trail augmentation.
Problem
Automatic generation of analog IC topologies is hard due to scarce public circuit data and ambiguous, non-scalable graph/text representations used by prior methods.
Approach
Represent each circuit as an undirected pin-level graph, serialize it as an Eulerian circuit (DFS with permuted neighbor exploration) starting from VSS, and pretrain a small GPT on these sequences to predict the next device pin, with augmentation expanding data about 70x.
Key results
- Data augmentation reduces validation loss by about 8.5x and increases the number of valid generated circuits by 73.5x versus unaugmented training.
- Model has 11.825M parameters (6 layers, 6 heads, vocab 1029, max length 1024) and is pretrained on a dataset of 3350 topologies spanning 11 circuit types, largest with 54 devices.
- Compared against CktGNN, LaMAGIC, and AnalogCoder on validity, scalability, novelty, and FoM across Op-Amps, bandgap references, and power converters.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| augment training sequences (3015 to 227766 sequences) (ablation) | AnalogGenie · Validation set | validation loss: approximately 8.5× reduction | Helped |
| augment training sequences (ablation) | AnalogGenie · Circuit generation | number of valid circuits: 73.5× | Helped |
Surprising findings
- Without augmentation the model overfits and fails to generate valid circuits.
Limitations
- Baselines were reproduced by following original works and adapted to pin-level evaluation, which may affect fairness.
- Performance evaluation relies on genetic-algorithm sizing and simulator-based FoM, limited to a few circuit types in reported results.
Experimental setup
Datasets: 3350 analog circuit topologies collected from public resources (textbooks/publications), manually drawn and netlisted
Benchmarks: generated topologies for Op-Amps, bandgap references, and power converters
Metrics: validity (simulatable) scalability (largest valid circuit, number of circuit types) novelty best FoM after sizing validation loss
Baselines: CktGNN LaMAGIC AnalogCoder
Builds on: GraphRNN CktGNN LaMAGIC AnalogCoder
Closest papers by meaning
- AnalogGenie-Lite: Enhancing Scalability and Precision in Circuit Topology Discovery through Lightweight Graph Modeling (ICML 2025 · similarity 0.93)
- AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding (NeurIPS 2026 · similarity 0.91)
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits (ICML 2024 · similarity 0.90)
- LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation (ICML 2025 · similarity 0.88)
- AnalogCoder: Analog Circuit Design via Training-Free Code Generation (AAAI 2025 · similarity 0.88)
- AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation (ICML 2025 · similarity 0.87)
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