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AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation

ICML 2025 · Large language models › Agents, code and math · approach: LLM-guided program synthesis · 0 citations (OpenAlex)

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Proposes AutoCircuit-RL, an instruction-tuned LLM refined with PPO against RoBERTa-based validity/efficiency/output-voltage reward models plus iterative adaptation, to generate analog power-converter topologies.

Problem

Analog circuit topology synthesis for power converters has a vast, sparse design space; existing search methods need many simulations and prior LLM approaches are limited to small circuits and lack performance-driven refinement.

Approach

Combine supervised instruction tuning of an LLM on incident-encoded netlists with PPO-based RL refinement using constraint-specific learned reward models (validity, efficiency, output voltage), followed by iterative adaptation on high-efficiency samples.

Key results

• Ac-Rl with Llama-3 reaches 75.11% classifier-estimated validity and 99.08% component-constraint success on 4-component circuits, versus 67.60% validity for the best prior baseline (Gumbel-Llama-3).
• Ac-Rl (Llama-3) achieves 80.90% efficiency-constraint success and 80.69% overall success on 4C/5C circuits, versus 69.56% and 71.27% for Gumbel-Llama-3.
• For 6-10 component circuits with k=1000 few-shot examples, Ac-Rl reaches 65.5% (6C) down to 58.5% (10C) overall success, versus 39.7% to 32.1% for prompt-tuned Flan-UL2.

Measured effects reported in the paper

Surprising findings

• Smaller fine-tuned models (GPT-Neo 2.7B, StableLM 3B) with the proposed method outperform much larger prompt-tuned 13B-20B models.
• Zero-shot and in-context learning produce mostly invalid netlist-like structures, so those results were excluded from the main table.

Limitations

• Evaluated only on power converter topologies with fixed component parameters and a single input voltage/frequency setting.
• Validity and efficiency are often measured by learned classifiers/regressors rather than only by simulator, and simulator-based success rates are lower than classifier-based ones.
• Performance drops as circuit size grows from 4-5 to 6-10 components, and larger-component results use few-shot fine-tuning on a different setup.

Experimental setup

Datasets: switching power converter netlist dataset (4-10 components, simulated with NGSpice)

Benchmarks: in-house switching power converter netlist dataset (4C, 5C, 6C-10C)

Metrics: circuit validity score circuit efficiency score duplicate generation rate success rate success rate@m

Baselines: Llama-2-13b prompt tuning Flan-UL2-20b prompt tuning GPT-Neo-2.7B fine-tuning StableLM-3B fine-tuning Llama-3-8B fine-tuning MPT-7B fine-tuning Gumbel-Max fine-tuning (CircuitSynth-Gumbel) GraphVAE

Builds on: PPO RLAIF RLHF Gumbel-Max trick Prompt tuning

Closest papers by meaning

• LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits (ICML 2024 · similarity 0.89)
• FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design (NeurIPS 2025 · similarity 0.88)
• LaMAGIC2: Advanced Circuit Formulations for Language Model-Based Analog Topology Generation (ICML 2025 · similarity 0.87)
• AnalogCoder: Analog Circuit Design via Training-Free Code Generation (AAAI 2025 · similarity 0.87)
• AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies (ICLR 2025 · similarity 0.87)
• Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization (ICLR 2024 · similarity 0.87)