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AnalogToBi: Device-Level Analog Circuit Topology Generation via Bipartite Graph and Grammar Guided Decoding

NeurIPS 2026 · Graph learning › Graph self-supervised learning · approach: Diffusion-based graph generation · 0 citations (OpenAlex)

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Proposes AnalogToBi, a GPT-style device-level analog topology generator that combines circuit-type conditioning, device renaming augmentation, a bipartite device-net graph representation, and grammar-guided decoding to reach high validity and novelty without HITL training.

Problem

Device-level analog circuit topology generation with transformers suffers from low electrical validity without human-in-the-loop training and memorization of training circuits caused by sequence-based pin-level representations.

Approach

Replace the device-pin token representation with a bipartite device-net graph serialized as a sequence, condition on circuit-type tokens, augment with random device renaming to break index memorization, and enforce pin/net structural rules via a state-machine grammar that masks invalid tokens during decoding.

Key results

Surprising findings

Limitations

Experimental setup

Datasets: AnalogGenie dataset (2,165 SPICE netlists)

Benchmarks: AnalogGenie dataset held-out circuits

Metrics: validity novelty valid & novel exact match graph edit distance type accuracy

Baselines: LaMAGIC AnalogGenie AnalogGenie-Lite AnalogGenie*

Builds on: AnalogGenie LaMAGIC grammar-constrained decoding

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