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ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design
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Releases ArchPower, an open-source dataset of 200 CPU samples (25 BOOM/XiangShan configurations x 8 workloads) with architecture-level features and gate-level-derived power labels, and benchmarks six architecture-level power models on it.
Problem
ML-based architecture-level CPU power modeling lacks open-source training and test data, because generating power labels requires full RTL implementation and VLSI power simulation flows, and existing in-house datasets omit SRAM or clock gating.
Approach
Generate realistic power labels for 25 BOOM and XiangShan configurations running 8 riscv-tests workloads through a full RTL-to-power flow (with clock gating and SRAM macros), pair them with 101 architectural features and per-component and per-power-group labels, and define Balance/Small/Large training-testing scenarios.
Key results
- PANDA achieves the best average total-power MAPE of 15.5% (R=0.96) across Balance/Small/Large scenarios on BOOM, versus 25.8% for McPAT-Plus on BOOM.
- McPAT-Calib reaches 8.2% MAPE on BOOM Balance but degrades to 50.6% (BOOM Large) and 90.0% (XiangShan Large), showing poor generalization outside training distribution.
- Under cross-workload 8-fold evaluation, McPAT-Calib attains the lowest MAPE (5.6% BOOM, 10.0% XiangShan), while analytical McPAT exceeds 400% MAPE.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use McPAT-Plus scaling instead of unscaled McPAT | McPAT power prediction · Balance, Small, and Large on BOOM and XiangShan | MAPE (%): >100 -> 18.1; >100 -> 29.6; >100 -> 31.0; >100 -> 21.6; >100 -> 28.2; >100 -> 28.3 | Helped |
| Replace total-power prediction with per-component models and sum component predictions (ablation) | McPAT-Calib · Total power, Balance on BOOM and XiangShan | MAPE (%): 8.2 -> 6.2; 33.2 -> 14.0 | Helped |
| Predict per-component power groups with separate models (ablation) | McPAT-Calib-Component · Total power, Balance, Small, and Large on BOOM and XiangShan | MAPE (%): 6.2 -> 6.2; 14.0 -> 15.0; 34.9 -> 35.3; 35.4 -> 36.0; 48.9 -> 49.2; 81.4 -> 80.5 | Mixed |
| Use PANDA instead of McPAT-Calib | Architecture-level total power prediction · Small and Large on BOOM and XiangShan | MAPE (%): 34.3 -> 29.2; 41.5 -> 23.9; 50.6 -> 10.4; 90.0 -> 26.3 | Helped |
| Train with configurations whose scale differs from the test configurations | ML-based architecture-level power models · Small and Large versus Balance | MAPE (%) | Hurt |
Surprising findings
- The enhanced McPAT-Calib variants and PANDA improve per-component accuracy but can hurt some components; e.g., RNU correlation drops to 0.64 for McPAT-Calib-CompGroup vs 0.90 for analytical models.
- Standard ML models (McPAT-Calib) degrade sharply when test configurations fall outside the training distribution (Small/Large scenarios).
Limitations
- Only two CPU architectures (BOOM and XiangShan) and 25 configurations, limiting diversity.
- Only 8 single-thread riscv-tests workloads, which are not very realistic.
- Labels come from one 40nm technology library; a 28nm variant is provided but FinFET is not covered.
Experimental setup
Datasets: riscv-tests workloads (dhrystone, median, multiply, qsort, rsort, towers, spmv, vvadd)
Benchmarks: ArchPower
Metrics: MAPE correlation coefficient R
Baselines: McPAT McPAT-Plus McPAT-Calib McPAT-Calib-Component McPAT-Calib-CompGroup PANDA
Builds on: McPAT McPAT-Calib PANDA gem5 Chipyard
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