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Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
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Introduces ChiPBench, an open-source benchmark of 20 real-world designs with full physical-implementation kits, and uses it to evaluate six AI-based chip placement algorithms by end-to-end PPA rather than intermediate surrogate metrics.
Problem
AI-based chip placement methods are evaluated with intermediate surrogate metrics (e.g., MacroHPWL) that often misalign with final design PPA (WNS, TNS, power, area), and existing benchmarks lack the design kits needed to run the full EDA flow.
Approach
Build a 20-circuit benchmark compiled from Verilog through OpenROAD with complete design kits, then plug each placement algorithm's output into the OpenROAD physical flow to measure end-to-end PPA and correlate it with intermediate metrics.
Key results
- WireMask-EA achieves the best MacroHPWL (0.647 normalized to OpenROAD) yet its TNS is 0.995 and area 1.004, while AutoDMP has best HPWL/congestion but TNS 1.540 relative to OpenROAD.
- On ariane133, AutoDMP reduces wirelength to 5694373 vs OpenROAD 6825071 but worsens WNS to -0.982 vs -0.498.
- MacroHPWL shows only weak correlation with final wirelength, WNS, TNS, area and power, while HPWL correlates strongly with final wirelength.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use AI-based macro placement instead of OpenROAD placement | Macro placement · Macro placement (benchmark aggregate) | MacroHPWL: 1.000 -> 0.647 | Helped |
| Use AI-based macro placement instead of OpenROAD placement | Macro placement · Macro placement (benchmark aggregate) | TNS: 1.000 -> 1.311 | Hurt |
| Use AI-based macro placement instead of OpenROAD placement | Macro placement · Macro placement (benchmark aggregate) | Power: 1.000 -> 1.013–1.062 | Mixed |
| Use DREAMPlace for cell placement instead of OpenROAD placement | Cell placement · Cell placement (benchmark aggregate) | HPWL: 1.000 -> 0.981 | Helped |
| Use DREAMPlace for cell placement instead of OpenROAD placement | Cell placement · Cell placement (benchmark aggregate) | WNS: 1.000 -> 1.321 | Hurt |
| Use AutoDMP for macro placement instead of OpenROAD placement | Macro placement · ariane133 | Wirelength: 6825071 -> 5694373 | Helped |
| Use AutoDMP for macro placement instead of OpenROAD placement | Macro placement · ariane133 | WNS: -0.498 -> -0.982 | Hurt |
| Use AutoDMP for macro placement instead of OpenROAD placement | Macro placement · ariane133 | TNS: -596.718 -> -1913.660 | Hurt |
| Optimize MacroHPWL as the placement indicator | Existing placement algorithms · Across evaluated designs | Wirelength correlation | No clear effect |
| Optimize HPWL as a placement surrogate | Placement algorithms · Across evaluated designs | Wirelength correlation | Helped |
Surprising findings
- Algorithms that best optimize MacroHPWL or HPWL often do not improve final timing; AI placers generally underperform OpenROAD on Power, TNS and Area.
- AutoDMP reduces wirelength but worsens timing because fewer buffers are inserted during timing repair.
Limitations
- Dataset contains only 20 circuits, which the authors acknowledge limits generalizability.
- Several academic placers required code modifications and produced errors (e.g., PDN, global placement divergence) when integrated into OpenROAD; ChiPFormer code needed fixes.
- Uses OpenROAD's native global and detailed placement and limited tools, which the authors note may constrain results.
Experimental setup
Datasets: ICCAD 2015 ISPD 2005 ISPD 2015 EPFL benchmarks OpenABC-D CircuitNet 2.0
Benchmarks: ChiPBench
Metrics: WNS TNS NVP power area wirelength MacroHPWL HPWL congestion Pearson correlation
Baselines: SA WireMask-EA DREAMPlace AutoDMP MaskPlace ChiPFormer OpenROAD TritonMacroPlacer
Builds on: DREAMPlace MaskPlace ChiPFormer OpenROAD
Closest papers by meaning
- See it to Place it: Evolving Macro Placements with Vision Language Models (NeurIPS 2026 · similarity 0.87)
- Chip Placement with Diffusion Models (ICML 2025 · similarity 0.87)
- Reinforcement Learning Policy as Macro Regulator Rather than Macro Placer (NeurIPS 2024 · similarity 0.86)
- EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation (ICML 2025 · similarity 0.86)
- Reinforcement Learning within Tree Search for Fast Macro Placement (ICML 2024 · similarity 0.85)
- CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design (ICLR 2025 · similarity 0.83)
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