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VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code

NeurIPS 2025 · Large language models › Language, safety and interpretability · approach: Data and evaluation methodology · 0 citations (OpenAlex)

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Predicts line-level congestion/timing and module-level WNS directly from Verilog by concatenating CL-Verilog-13B hidden-state embeddings of lines, neighbors, and modules, then classifying with XGBoost/LightGBM.

Problem

Early-stage prediction of design-quality metrics (timing violations and routing congestion) at individual line-of-code granularity directly from Verilog RTL, which prior work did only at module level and mostly via intermediate representations like AIGs.

Approach

Use penultimate/last-layer hidden-state embeddings from a Verilog-specialized code LLM (CL-Verilog) for each line and for the whole module, reduce them with an encoder, concatenate with neighboring-line embeddings (context window p), and train gradient-boosted tree classifiers/regressors for line-level labels and min-over-lines module WNS.

Key results

• Line-level F1 of 0.86 for congestion and 0.95 for timing using LightGBM with context length 5.
• Module-level timing MAPE of about 0.06 with R2 0.94 for VeriLoC versus 0.12-0.15 MAPE for RTL-Timer and MasterRTL baselines.
• Prompted GPT-4o identified no congestion-causing lines in any trial and produced many false positives for timing.

Measured effects reported in the paper

Surprising findings

• Prompting GPT-4o failed to localize congestion-causing lines in any trial, indicating black-box LLMs do not transfer to hardware line-level quality prediction.
• Timing prediction achieved F1 0.83 even without neighboring-line context, suggesting timing depends less on local context than congestion.

Limitations

• Operates only on leaf modules from OpenABCD and has not been tested on industrial designs with inter-module dependencies.
• Relies on labels generated by Synopsys RTL Architect with a single aggressive timing constraint and Nangate 45nm library.

Experimental setup

Datasets: OpenABCD

Benchmarks: OpenABCD

Metrics: F1 precision recall R2 MAPE

Baselines: MasterRTL RTL-Timer VeriDistill GNN-based netlist predictor GPT-4o CircuitFusion VeriLoC-mod FNN head

Builds on: CL-Verilog XGBoost LightGBM MasterRTL RTL-Timer

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