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PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Boards (PCB) Schematic Design with Structured Verification

NeurIPS 2026 · Large language models › Reasoning and chain of thought · approach: Test-time compute scaling · 0 citations (OpenAlex)

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Training-free inference-time framework that turns a frozen LLM into a PCB schematic generator (SKiDL code) using a schema-induced IC knowledge graph, a deterministic 5-layer continuous-reward verifier, and a Thompson Sampling refinement bandit, evaluated on two new PCB benchmarks.

Problem

LLM code synthesis for PCB schematic design lacks unit-test oracles and golden references, and existing EDA/analog verifiers (e.g., SPICE) do not check schematic-level correctness under real IC pin and package constraints.

Approach

Combine a datasheet-induced pin-role knowledge graph for grounding decoding, a deterministic layered structural verifier that returns dense pin-localized rewards in [0,1], and an arm-acquiring Thompson Sampling bandit with reward-informed Beta priors and adaptive temperature for refinement.

Key results

• Gemma-4-31B with the framework reaches 81.3% Pass@1 on PCBBench overall (47.1% Hard) versus 41.9% (10.2% Hard) for the Circuitron baseline on the same backbone.
• On held-out Open-Schematics-Eval, GPT-5.4 reaches 79.3% Pass@1 overall (70.7% Hard) with zero verifier code changes.
• Verifier agreement with a senior PCB engineer on N=300 gives Cohen's kappa=0.91, with 6.7% false accept and 2.7% false reject.

Surprising findings

• Removing the schema-induced KG drops Gemma-4-31B Hard pass rate from 47.1% to 2.0%, the largest single component effect.
• The no-refinement Pass@4 baseline reaches 60.5% overall while arm-selection policies differ by only about 2.9pp, suggesting the refinement loop dominates over the choice of bandit policy.

Limitations

• Verifier false-accept rate of 6.7% and ERC over-rejection contribute to reported pass rates; lower-bound corrected numbers are reported.
• Regret bound is a heuristic scaling argument and not a finite-sample guarantee at T=4.
• Small-model (InternLM3-8B) collapses on Hard tasks, indicating a model-capacity floor.

Experimental setup

Datasets: PCBBench Open-Schematics-Eval open-schematics dataset IC vendor datasheets

Benchmarks: PCBBench Open-Schematics-Eval

Metrics: Pass@1 Pass@5 Wilson 95% CI Cohen's kappa false accept rate false reject rate

Baselines: Circuitron Self-Refine Reflexion epsilon-greedy UCB1 Greedy best-mean arm Pass@4 i.i.d. sampling

Builds on: REx Circuitron SKiDL VF2

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