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QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation
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Introduces CodeV-R1, an RLVR framework for Verilog generation combining a rule-based testbench generator, round-trip NL-code data synthesis with equivalence checking, distillation from DeepSeek-R1, and adaptive DAPO, yielding a 7B model that matches or beats DeepSeek-R1 on RTLLM.
Problem
RLVR for Verilog generation from natural-language specs is hampered by the lack of accurate automated verification for hardware designs, scarcity of high-quality NL-code pairs, and high RL training cost.
Approach
A rule-based testbench generator built on circuit-structure analysis (ports, clocks, resets) gives accurate equivalence rewards; round-trip code->NL->code synthesis filters NL-code pairs by equivalence; distill-then-RL training; and an adaptive DAPO that sets generation batch size from the observed valid-sample ratio to cut sampling cost.
Key results
- CodeV-R1-7B achieves 68.8% pass@1 on VerilogEval v2 spec-to-RTL and 72.9% pass@1 on RTLLM v1.1, above DeepSeek-R1-671B's 64.8% on RTLLM v1.1.
- Testbench misclassifies 0.3% of golden-vs-golden cases versus 7.6% for the DeepSeek-V3-generated testbench (96.1% fewer false negatives).
- Adaptive DAPO yields a 1.25x training speedup over baseline DAPO.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · RTLLM v1.1 | pass@1: 57.4 -> 72.9 | Helped |
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · VerilogEval v1 Machine | pass@1: 76.2 -> 76.5 | Mixed |
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · VerilogEval v1 Human | pass@1: 65.7 -> 69.9 | Helped |
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · VerilogEval v2 SR | pass@1: 65.2 -> 68.8 | Helped |
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · VerilogEval v2 CC | pass@1: 65.5 -> 69.9 | Helped |
| add RL fine-tuning after distillation (ablation) | CodeV-R1-7B · RTLLM v2 | pass@1: 57.2 -> 68.0 | Helped |
| remove difficulty filtering from the RL dataset (ablation) | CodeV-R1-7B RL training · RL training | response length during training | Hurt |
| remove round-trip equivalence checking and use pseudo-golden code (ablation) | CodeV-R1-7B RL training · RL training | reward | Hurt |
| adapt generation batch size to valid-sample rates | DAPO · RL training | speedup: 1.25× | Helped |
| use rule-based testbench generation instead of DeepSeek-V3-generated testbenches | Verilog equivalence testbench · Golden-vs-golden classification | false-negative rate: 7.6% -> 0.3% | Helped |
| use rule-based testbench generation instead of DeepSeek-V3-generated testbenches | Verilog equivalence testbench · Sequential-circuit fuzzing | injected-error detection rate: 40% -> 65% | Helped |
| increase the response-length budget from 4096 to 16384 tokens | CodeV-R1-7B · RTLLM v1.1 | accuracy: 7.1% to 72.9% | Helped |
Surprising findings
- Despite being distilled from DeepSeek-R1, the RL-trained 7B model outperforms DeepSeek-R1-671B on RTLLM v1.1 and v2 while still trailing it on most VerilogEval splits.
- Distilling general math/code reasoning from larger models did not improve Verilog capability of smaller models.
Limitations
- No error bars or statistical significance tests due to RL training cost.
- Weak on table/graph (Karnaugh map, FSM, waveform) problems in VerilogEval v2, and higher runtime errors than DeepSeek-R1.
- Testbench relies on Icarus Verilog simulation and randomized inputs, with residual misclassification (0.3%).
Experimental setup
Datasets: GitHub Verilog snippets VerilogEval v1 VerilogEval v2 RTLLM v1.1 RTLLM v2
Benchmarks: VerilogEval v1 VerilogEval v2 RTLLM v1.1 RTLLM v2
Metrics: pass@1 pass@5 pass@10 error rate false negative rate
Baselines: DeepSeek-R1-671B DeepSeek-V3-671B QwQ-32B DeepSeek-R1-Distill-Qwen-32B DeepSeek-R1-Distill-Qwen-7B Qwen2.5-Coder-32B-Instruct Qwen2.5-Coder-7B-Instruct GPT-4o RTLCoder BetterV CodeV CraftRTL
Builds on: DAPO DeepSeek-R1 verl LLaMAFactory Yosys
Closest papers by meaning
- QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation (NeurIPS 2025 · similarity 0.90)
- Rethinking Verification for LLM Code Generation: From Generation to Testing (NeurIPS 2025 · similarity 0.89)
- Reinforcement Learning for Reasoning in Large Language Models with One Training Example (NeurIPS 2025 · similarity 0.89)
- Reinforcement Learning with Verifiable Rewards Implicitly Incentivizes Correct Reasoning in Base LLMs (ICLR 2026 · similarity 0.89)
- RL Tango: Reinforcing Generator and Verifier Together for Language Reasoning (NeurIPS 2025 · similarity 0.88)
- R1-Code-Interpreter: LLMs Reason with Code via Supervised and Multi-stage Reinforcement Learning (ICLR 2026 · similarity 0.88)
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