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Towards Next-Generation Logic Synthesis: A Scalable Neural Circuit Generation Framework
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Revisits differentiable neural architecture search (DNAS) for exact circuit generation from truth tables and proposes T-Net, a triangle-shaped regularized circuit network with multi-label data transformation, plus an RL-restart evolutionary algorithm for circuit optimization that beats IWLS 2022/2023 winners.
Problem
Generating exactly correct, compact logic circuits from input-output examples (truth tables) with differentiable neural architecture search struggles on large circuits and is sensitive to hyperparameters.
Approach
Diagnoses three DNAS failure modes (skip-connection overfitting, mismatch with circuit triangular structure, imbalanced per-example difficulty) and addresses them with Shannon-decomposition multi-label data transformation, a triangle-shaped NAND-gate network, a layer-weighted skip regularizer, and a hardness-aware loss; optimization uses an EA whose individuals are improved by an RL operator-seque
Key results
- T-Net achieves 100% generation accuracy on 17 of 18 circuits and at least 99.9% on all, versus 82.51% average for Basic DNAS.
- Optimized circuits average 68.70% fewer nodes than SOP+resyn2 across 10 circuits in Table 3.
- Optimized circuits beat the IWLS 2023 first-place Google DNAS result by 5.36% on average node count.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| replace DNAS Skip with T-Net | circuit generation · 10 circuits in Table 1 | accuracy: 91.99 -> 99.99 | Helped |
| replace SOP + resyn2 with T-Net + resyn2 | circuit generation · 10 circuits in Table 2 | nodes: 366.39 -> 230.06 | Helped |
| use T-Net with EA/RL instead of Google (AI) | circuit optimization · 10 circuits in Table 3 | nodes: 88.06 -> 83.33 | Helped |
| decompose the truth table | T-Net · LogicNets6 | accuracy: 99.60 -> 100 | Helped |
| decompose the truth table | T-Net · Espresso9 | wrong bits: 61 -> 6 | Helped |
| add regularized skip-connection (ablation) | DNAS circuit generation · LogicNets2 | accuracy: 79.40 -> 99.91 | Helped |
| add Boolean hardness-aware loss (ablation) | DNAS with regularized skip-connection · LogicNets2 | wrong bits: 10 -> 0 | Helped |
| add triangle-shaped architecture (ablation) | DNAS with regularized skip-connection and hardness-aware loss · LogicNets2 | nodes: 281 -> 273 | Helped |
| add regularized skip-connection (ablation) | DNAS circuit generation · Arithmetic2 | accuracy: 94.97 -> 99.33 | Helped |
| add Boolean hardness-aware loss (ablation) | DNAS with regularized skip-connection · Arithmetic2 | wrong bits: 12 -> 0 | Helped |
| add triangle-shaped architecture (ablation) | DNAS with regularized skip-connection and hardness-aware loss · Arithmetic2 | nodes: 263 -> 254 | Helped |
Surprising findings
- DNAS shows up to 14.5% accuracy variation depending only on random seed.
- Most DNAS-generated circuits (14 of 16) failed to be generated exactly.
Limitations
- Existing DNAS baseline re-implemented since Google did not release code.
- Sensitivity analysis limited to random seed and initial network size.
- Decomposition variable selection done by SOP-based trial, not a general rule.
Experimental setup
Datasets: Espresso LogicNets Random Arithmetic
Benchmarks: Espresso LogicNets Random Arithmetic IWLS 2022 IWLS 2023
Metrics: accuracy wrong bits AIG node count logic level training time
Baselines: Basic DNAS DNAS Skip Darts- SOP resyn2 IWLS 2022 teams (TUW, UCB, EPFL) IWLS 2023 teams (NBU, EPFL, TUW, Google)
Builds on: DNAS for logic synthesis (Belcak et al.) differentiable logic gate networks DARTS- Gumbel-softmax ABC
Closest papers by meaning
- Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization (ICLR 2024 · similarity 0.89)
- A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design (ICML 2024 · similarity 0.88)
- Circuit Transformer: A Transformer That Preserves Logical Equivalence (ICLR 2025 · similarity 0.86)
- LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits (ICML 2024 · similarity 0.86)
- AUTOCIRCUIT-RL: Reinforcement Learning-Driven LLM for Automated Circuit Topology Generation (ICML 2025 · similarity 0.86)
- AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies (ICLR 2025 · similarity 0.86)
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