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An And-Sum Circuit with Signed Edges That Is More Succinct than SDD

AAAI 2025 · Graph learning › Knowledge and temporal graphs · approach: Logical query answering and rule reasoning · 0 citations (OpenAlex)

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Introduces structured Decomposable And-Sum Circuits (st-DASCs), which replace OR nodes with signed-edge sum nodes so logical negation is poly-time, and shows they are more succinct than st-d-DNNFs (hence SDDs) while supporting SDD's knowledge-compilation-map operations.

Problem

Existing knowledge compilation languages trade off succinctness against tractability: st-d-DNNFs are more succinct than SDDs but lack operations such as logical negation, bounded disjunction and single forgetting that SDDs support.

Approach

Replace OR nodes with sum nodes whose edges carry signs in {-1,1} and AND nodes with min/product semantics, so that negation is a constant-size transformation (a + node with a -1 edge and a constant 1); the resulting structured decomposable circuit is shown to be more succinct than st-d-DNNF and to support SDD's polytime operations.

Key results

Measured effects reported in the paper

What was changedWhereMeasuredEffect
Replace deterministic OR nodes with signed sum nodes and add signed edgesst-DASC · Boolean function representations; comparison with st-d-DNNFsuccinctnessHelped
Add signed edges to enable logical negationst-DASC · Knowledge compilation map operations; comparison with SDDtractable operation supportHelped

Surprising findings

Limitations

Experimental setup

Baselines: SDD st-d-DNNF OBDD d-DNNF

Builds on: st-d-DNNF SDD knowledge compilation map

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