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Rethinking Circuit Completeness in Language Models: AND, OR, and ADDER Gates
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Introduces AND, OR, and ADDER logic gates to decompose circuits, and proposes an Ns+Dn (noising plus denoising intervention) framework that recovers OR gates and yields more complete, faithful, and less random circuits in GPT-2 small.
Problem
Circuit discovery methods based on noising-based intervention lack completeness because they only partially recover OR gates (redundant parallel paths), making circuits unstable across runs and omitting key mechanisms.
Approach
Decompose circuits into AND, OR, and ADDER logic gates via the intersection of noising-based (Ns) and denoising-based (Dn) circuits, and run both interventions in parallel within existing circuit discovery methods so OR gates are recovered and gate types separated, at roughly at most 2x cost.
Key results
- Ns+Dn circuits show lower Hamming-distance randomness than Ns circuits across sparsity levels (e.g., ACDC on IOI at 100 edges: 3.4 vs. Ns-only baseline difference reported in the table)
- Completeness evaluation: circuits removed via Ns+Dn perform noticeably worse than Ns-only circuits in KL divergence and accuracy, with the largest gap for EAP
- Faithfulness relationship reported as Ns+Dn approximately equal to Ns, both greater than Dn
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Add denoising-based intervention (Dn) to noising-based intervention (Ns) | Circuit discovery methods ACDC, EAP, and EdgePruning · IOI, GT, and syntactic agreement | Completeness | Helped |
| Add Dn to Ns | ACDC, EAP, and EdgePruning circuits · IOI | Faithfulness (KL divergence and accuracy) | No clear effect |
| Use Dn instead of Ns | Circuit discovery methods · IOI, GT, and syntactic agreement | Faithfulness | Hurt |
| Ablate either single edge in the AND gate (ablation) | GPT2-small AND gate · AND gate | Δ KL: 0.50 (1) -> 0.02 (0); 0.50 (1) -> 0.04 (0) | Hurt |
| Ablate either single edge in the OR gate (ablation) | GPT2-small OR gate · OR gate | Δ KL: 0.28 (1) -> 0.27 (1) | No clear effect |
| Ablate either single edge in the ADDER gate (ablation) | GPT2-small ADDER gate · ADDER gate | Δ KL: 0.65 (2) -> 0.32 (1); 0.65 (2) -> 0.36 (1) | Hurt |
| Ablate both edges (ablation) | GPT2-small AND, OR, and ADDER gates · AND, OR, and ADDER gates | Δ KL: 0.50 (1) -> 0.00 (0); 0.28 (1) -> 0.00 (0); 0.65 (2) -> 0.00 (0) | Hurt |
| Remove two edges rather than one (ablation) | ADDER gates · Indirect Object Inference (IOI) | Δ KL | Hurt |
Surprising findings
- Linear estimation (EAP) fails to recover any OR-gate edges under Ns because other edges remain in clean state, causing small per-edge effects
Limitations
- Only other gate types like XOR are not captured by the Ns/Dn intersection
- Gate decomposition relies on aligning edge counts between Ns and Dn circuits via a misalignment score
- Evaluated only on GPT-2 small and three tasks
Experimental setup
Datasets: IOI greater than (GT) subject-verb agreement (SA)
Benchmarks: IOI greater than subject-verb agreement
Metrics: KL divergence accuracy Hamming distance faithfulness completeness sparsity
Baselines: ACDC EAP EdgePruning
Builds on: ACDC EAP EdgePruning interchange intervention
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