Research map / Architectures and efficiency / RNNs and normalization
NeuralSteiner: Learning Steiner Tree for Overflow-avoiding Global Routing in Chip Design
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Proposes NeuralSteiner, which predicts candidate Steiner/corner points with a ResNet-34 plus recurrent crisscross attention network and builds overflow-avoiding rectilinear Steiner trees via a net augmented graph, cutting global routing overflow by up to 99.8%.
Problem
Learning-based global routing generates rectilinear Steiner trees with considerable congestion overflow, which hinders practical use in chip design.
Approach
Predict candidate Steiner and corner points as a pixel-level segmentation map using a ResNet with recurrent crisscross attention and an overflow-aware loss, then build a net augmented graph over predicted points and greedily construct an RST that minimizes a wirelength-plus-overflow weight, avoiding the stripe mask that limits congestion avoidance in HubRouter.
Key results
- On ISPD07, overflow reduced by an average of 97.8% vs HubRouter (GAN) across eight designs, up to 99.8% on adaptec04_2d, with wirelength increase within 1.8%.
- On ISPD98 ibm01-06, overflow reduced by an average of 61.1% vs HubRouter (GAN) with wirelength within 1.8%; NeuralSteiner has 18 overflow on ibm05.
- Integrating NeuralSteiner into CUGR reduced DRC shorts by 4.4% and spaces by 19.1% on average with minimal wirelength and via change.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| use NeuralSteiner instead of HR-GAN | global routing · ISPD07, eight chip designs | overflow: average reduction of 97.8%; up to a 99.8% reduction | Helped |
| use NeuralSteiner instead of HR-GAN | global routing · ISPD07, eight chip designs | wirelength: within 1.8% | Hurt |
| add neural network-predicted candidate points (ablation) | NeuralSteiner · adaptec05_2d | overflow: 10905 -> 431 | Helped |
| add overflow loss ℓof (ablation) | NeuralSteiner · adaptec05_2d | overflow: 2795 -> 431 | Helped |
| add RCCA module (ablation) | NeuralSteiner · adaptec05_2d | overflow: 2290 -> 431 | Helped |
| replace HubRouter's hub-pin connection and stripe mask with NAG-based RST construction (ablation) | HubRouter (GAN) · adaptec05_2d | overflow: 102108 -> 5245 | Helped |
| use NAG-based post-processing without predicted candidate points (ablation) | HubRouter (GAN) · adaptec05_2d | overflow: 5245 -> 431 | Hurt |
Limitations
- Still relies on heuristic post-processing (greedy NAG-based RST construction), which is time-consuming and adds slight wirelength.
- Generation time is slower than HubRouter on small nets due to recurrent crisscross attention; RST construction complexity is high in the worst case.
- Candidate points are binary rather than continuous probability maps, and the pipeline is not end-to-end.
Experimental setup
Datasets: ISPD07 ISPD98 ISPD18 ISPD19
Benchmarks: ISPD98 ibm01-06 ISPD07 adaptec01-05_2d, newblue01-03_2d ISPD18/19 (post-detailed routing via CUGR+NeuralSteiner)
Metrics: total overflow wirelength running time connectivity correctness rate short and space violations
Baselines: HubRouter (GAN) HubRouter (VAE) HubRouter (DPM) GeoSteiner FLUTE + Edge Shifting Boxrouter PRNet CUGR
Builds on: HubRouter CUGR RCCA FLUTE
Closest papers by meaning
- DSBRouter: End-to-end Global Routing via Diffusion Schr\"{o}dinger Bridge (ICML 2025 · similarity 0.90)
- NN-Steiner: A Mixed Neural-Algorithmic Approach for the Rectilinear Steiner Minimum Tree Problem (AAAI 2024 · similarity 0.87)
- PreRoutGNN for Timing Prediction with Order Preserving Partition: Global Circuit Pre-training, Local Delay Learning and Attentional Cell Modeling (AAAI 2024 · similarity 0.85)
- A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design (ICML 2024 · similarity 0.83)
- EGPlace: An Efficient Macro Placement Method via Evolutionary Search with Greedy Repositioning Guided Mutation (ICML 2025 · similarity 0.83)
- DeepLayout: Learning Neural Representations of Circuit Placement Layout (ICML 2025 · similarity 0.83)
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