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RAM-Net: Linear-Time Sequence Modeling with Sparsely Addressable State

NeurIPS 2026 · Architectures and efficiency › Attention and transformers · approach: State space and recurrent sequence models

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Proposes RAM-Net, a fixed-size slot-array recurrent state accessed via sparse product-softmax address decoding with Top-K selection, gated sparse updates and cyclic address positional embeddings, achieving strong long-context retrieval and perplexity at 340M/1.3B scales with far fewer state elements accessed per step.

Problem

Linear attention compresses history into one shared recurrent state, so information from different tokens superposes, causing inter-token interference that degrades fine-grained long-range recall; enlarging the state also raises per-step access cost.

Approach

Organize the recurrent state as a fixed array of independent slots and let each key/query select a sparse Top-K set of slots via a Product Softmax address decoder (computed by exact prefix-tree search), with a gated sparse update that writes and forgets only addressed slots, plus cyclic address positional embedding.

Key results

Surprising findings

Limitations

Experimental setup

Datasets: FineWeb-Edu RULER S-NIAH MQAR (Zoology) WikiText-103 LAMBADA MMLU ARC OpenBookQA SciQ COPA PIQA HellaSwag

Benchmarks: WikiText-103 LAMBADA MMLU ARC-e ARC-c OpenBookQA SciQ boolQ COPA PIQA HellaSwag WinoGrande

Metrics: perplexity accuracy decoding throughput per-step active state size

Baselines: Transformer++ Mamba2 GLA GSA Gated DeltaNet DeltaNet Linear attention SWA H3

Builds on: Gated DeltaNet Mamba2 GLA GSA RoPE Flame

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