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AtomNet: Designing Tiny Models from Operators Under Extreme MCU Constraints
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Builds AtomDB, a database of per-operator latency, SRAM and Flash measurements on MCUs, derives guidelines from it, and uses them to design AtomNet, a hybrid-block tiny model searched by MACs with a zero-cost proxy.
Problem
Designing ImageNet-accuracy models that fit extreme MCU constraints (SRAM, Flash, latency) without customized inference libraries or costly NAS searches.
Approach
Measure massive atomic operators (fused kernels) on real MCU hardware to form AtomDB, derive operator-level guidelines on Flash, SRAM and latency, lift them to blocks and stages to build a hybrid block pattern (SEP in early SRAM-bound stages, ConvNext in later Flash-bound stages), and search with MACs as a zero-cost accuracy proxy.
Key results
- AtomNet reaches 66.7% ImageNet Top-1 on STM32F412 (256KB SRAM/1MB Flash) and 73.0% on STM32H743 (512KB SRAM/2MB Flash), outperforming MCUNetV2 by 1.5% and 1.2%.
- Ours-320KB achieves 64.6% Top-1 at 367ms on STM32F746 versus MCUNet-320KB 61.8% at 433ms.
- AtomNet reaches 95.0% on VWW with 512KB SRAM, versus MCUNetV2 94.0%.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use the proposed AtomNet design rather than MCUNetV2-M4 | AtomNet on STM32F412 · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 64.9% -> 66.7% | Helped |
| Use the proposed AtomNet design rather than MCUNet-320KB | AtomNet on STM32F746 · ImageNet, 320KB SRAM/1MB Flash | Top-1 accuracy: 61.8% -> 64.6% | Helped |
| Use the proposed AtomNet design rather than MCUNetV2-H7 | AtomNet on STM32H743 · ImageNet, 512KB SRAM/2MB Flash | Top-1 accuracy: 71.8% -> 73.0% | Helped |
| Replace the hybrid block pattern with MBConv-only blocks (ablation) | AtomNet · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 66.7% -> 60.8% | Hurt |
| Replace the hybrid block pattern with ConvNext-only blocks (ablation) | AtomNet · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 66.7% -> 63.8% | Hurt |
| Replace the hybrid block pattern with SEP-only blocks (ablation) | AtomNet · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 66.7% -> 65.6% | Hurt |
| Use EA search instead of the default search (ablation) | Hybrid AtomNet · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 66.7% -> 66.6% | No clear effect |
| Use the Flash-friendly design with depth-wise convolution rather than the NC-based ResNet design | ImageNet model under Flash constraint · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 61.6% -> 64.0% | Helped |
| Replace MBConv with SEP without SE in SRAM-dominant stages | TinyNet-E-style model · ImageNet, 256KB SRAM/1MB Flash | SRAM: 270KB -> 217KB | Helped |
| Use more ConvNext blocks while satisfying SRAM and Flash constraints instead of using only MBConv blocks | Ours-256KB · ImageNet, 256KB SRAM/1MB Flash | Latency: 368ms -> 275ms | Helped |
| Combine SEP in early stages with ConvNext in later stages rather than using a single block type (ablation) | AtomNet · ImageNet, 256KB SRAM/1MB Flash | Top-1 accuracy: 60.8%, 63.8%, 65.6% -> 66.7% | Helped |
Surprising findings
- No single block type is best on latency, SRAM and Flash simultaneously, motivating the hybrid pattern.
- A simple MACs-based zero-cost search matches or beats the costly evolutionary search variant (66.7% vs 66.6% Top-1 for Hybrid-EA at ~100h).
Limitations
- Relies on MACs as zero-cost accuracy proxy, which is not validated per-task beyond the reported searches.
- Latency gains are reported for specific STM32 hardware and inference libraries, with the paper's own hardware-specific guidelines.
Experimental setup
Datasets: ImageNet VWW Pascal VOC AtomDB
Benchmarks: ImageNet VWW Pascal VOC
Metrics: Top-1 accuracy latency SRAM Flash mAP MACs
Baselines: MCUNet-256KB MCUNet-320KB MCUNet-512KB MCUNetV2 MobileNetV1 0.5x MobileNetV2 0.35x ProxylessNAS 0.3x TinyNet-E PPLCNet ResNet
Builds on: MCUNet MCUNetV2 ConvNeXt MobileNet TinyEngine
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