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AI-Powered Algorithm-Centric Quantum Processor Topology Design
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Qtailor uses PPO-based reinforcement learning with a reward-replay mechanism to design quantum processor topologies tailored to individual circuits (degree ≤4), then uses force-directed grid layout to make them manufacturable, reducing mapped circuit depth versus Qiskit/SABRE.
Problem
Qubit mapping for quantum circuits is constrained to fixed processor topologies, and the topology itself strongly affects mapped circuit depth; the paper asks whether tailoring the topology to each circuit reduces depth on noisy processors.
Approach
Treat the qubit coupling graph as the RL environment: an agent (PPO) incrementally adds edges between qubit pairs under a degree-4 constraint, rewarded by mapped-circuit depth change via Qiskit; a reward-replay memory caches action-level rewards to cut costly compilation calls, and a force-directed grid layout makes the resulting topology grid-like with fewer crossings.
Key results
- Qtailor reduces mapped circuit depth by 5% to 46% relative to Qiskit/SABRE, with over 60% of samples showing at least 20% reduction.
- On 6-qubit circuits scaling from 60 to 210 gates, depth reduction grows from 31.03% to 40.74%.
- Reward-replay reduces the sampling cost and PPO convergence is reported 24% faster; the paper also reports gate reduction of 4.78% to 36.39%.
Measured effects reported in the paper
| What was changed | Where | Measured | Effect |
|---|---|---|---|
| Use Qtailor's circuit-specific topology instead of Qiskit's fixed grid topology | Quantum circuit mapping · MQT Bench circuits | depth: 5% to 46% | Helped |
| Use Qtailor's circuit-specific topology instead of Qiskit's fixed grid topology | Quantum circuit mapping · MQT Bench circuits | total gates: 4.78% to 36.39% | Helped |
| Optimize the topology to reduce gate count with Qtailor | Quantum circuit execution · 10-qubit circuits | fidelity: 10.91% | Helped |
| Use Qtailor's suggested topology instead of the fixed grid | Quantum circuit mapping with Tket · Circuits evaluated with Tket | depth: 39% | Helped |
| Increase circuit gate count while using Qtailor's topology | Qtailor · 6-qubit circuits, 60 to 210 gates | depth reduction versus Qiskit: 31.03%, 31.52%, 33.87% , 39.11%, 39.65% and 40.74% | Helped |
| Add reward replay to PPO (ablation) | PPO · Topology-design training | training convergence time: 24% | Helped |
| Add reward replay to PPO (ablation) | PPO · Topology-design training | loss | No clear effect |
Surprising findings
- Minor edge differences between non-isomorphic graphs change circuit depth substantially (e.g., 211 vs 137 for QFT with one added edge).
Limitations
- Only connectivity constraints are modeled; other physical constraints (different fabrication, quantum systems) are not considered.
- Reward replay approximates r(s,a) by r(a), which may introduce inaccuracy.
- Evaluation uses noiseless or simulated depth and fidelity rather than real hardware results.
Experimental setup
Datasets: MQT Bench
Benchmarks: MQT Bench circuits (qnn, vqe, ae, ansatz, su2, QFT)
Metrics: circuit depth idle ratio total gate count fidelity
Baselines: Qiskit (SABRE) Tket
Builds on: PPO SABRE force-directed layout MQT Bench
Closest papers by meaning
- TensorRL-QAS: Reinforcement learning with tensor networks for improved quantum architecture search (NeurIPS 2025 · similarity 0.89)
- Curriculum reinforcement learning for quantum architecture search under hardware errors (ICLR 2024 · similarity 0.88)
- QCircuitBench: A Large-Scale Dataset for Benchmarking Quantum Algorithm Design (NeurIPS 2025 · similarity 0.87)
- Equivariant Reinforcement Learning for Clifford Quantum Circuit Synthesis (NeurIPS 2026 · similarity 0.86)
- Replay-buffer engineering for noise-robust quantum circuit optimization (NeurIPS 2026 · similarity 0.86)
- MG-Net: Learn to Customize QAOA with Circuit Depth Awareness (NeurIPS 2024 · similarity 0.86)
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