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Pipeline Parallelism with Controllable Memory

NeurIPS 2024 · Architectures and efficiency › RNNs and normalization · approach: Distributed LLM inference systems · 5 citations (OpenAlex)

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Proposes a building-block framework for pipeline schedules showing peak activation memory is set by building-block lifespan, and introduces V-shape schedules (V-Min, V-Half, V-ZB) with controllable memory that cut activation memory to about 1/3 or 1/2 of 1F1B.

Problem

Synchronous pipeline parallelism suffers from pipeline bubbles and large activation memory, and existing schedules lack a systematic methodology for controlling peak memory.

Approach

Decompose pipeline schedules as a repeating building block whose lifespan determines peak activation memory; use V-shape placement (2 stages per device, reversed second half) with split B/W backward passes and controlled offsets to balance and reduce memory while keeping bubbles low.

Key results

Measured effects reported in the paper

What was changedWhereMeasuredEffect
Use V-ZB instead of 1F1BPipeline schedule for 98.5B training · Sequence length 1024, batch size 160MFU (%): 54.77 -> 63.31Helped
Use V-Half instead of 1F1BPipeline schedule for 98.5B training · Sequence length 3072, batch size 640MFU (%): 62.95 -> 66.34Helped
Use V-Half instead of 1F1B-RPipeline schedule for 98.5B training · Sequence length 16384, batch size 160MFU (%): 42.05 -> 57.85Helped
Use V-Min instead of 1F1BPipeline schedule for 9.6B training · 16 GPUs, microbatch 4, 16 microbatchesActivation memory (GB): 46 -> 19Helped
Use V-Half instead of 1F1B-RPipeline schedule for 9.6B training · 16 GPUs, microbatch 4, 16 microbatchesMFU (%): 24.5 -> 38.3Helped
Use V-Min rather than V-HalfV-Shape pipeline schedules · Theoretical schedule, asymptoticPeak activation memory: ≈ M/2 -> ≈ M/3Helped
Use V-Min rather than V-HalfV-Shape pipeline schedules · When F, B, and W have different run times and microbatch count growsBubble rateHurt
Use V-ZB rather than V-HalfV-Shape pipeline schedules · 98.5B, sequence length 3072, batch size 640MFU (%): 62.56 vs 66.34Hurt

Surprising findings

Limitations

Experimental setup

Metrics: MFU peak activation memory throughput (samples per second per GPU) bubble rate

Baselines: 1F1B interleaved 1F1B 1F1B-R ZB-1P ZB-2P

Builds on: 1F1B Zero Bubble pipeline parallelism Megatron-LM interleaved 1F1B GPipe

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